In today's technologies, it is critical to monitor power supply conditions (e.g., voltage level variations and/or noise) in a system due primarily to the negative impact of such conditions on performance and integrity of the system. These conditions, however, are often difficult to estimate accurately during a design phase due at least in part to their strong dependence on various parasitic elements, both on-chip and off-chip, as well as process dependence of local switching activity.
Supply noise has become a serious problem in recent IC designs. This problem is exacerbated with the use of lower power supply voltage levels (e.g., 1.2 volts or less) and increased current consumption, among other factors. Many digital power supplies are noisy enough to make high-speed interfaces and other circuitry, including, for example, double data rate (DDR) and serializer/deserializer (Serdes) circuitry, fail. Decoupling capacitance mitigates dynamic power supply fluctuations. However, such decoupling capacitance significantly increases the amount of chip area required by an IC design and is therefore undesirable (or impractical). Furthermore, excessive decoupling capacitance, typically implemented in an IC using metal-oxide-semiconductor (MOS) transistors, results in severe gate leakage in advanced IC fabrication technologies. Although the use of adequate power supply wiring may help reduce power supply noise, wiring resources are often limited and excessive amounts of power supply wiring makes signal routing difficult, particularly for dense IC designs.
Power consumption in high-end ICs and systems-on-chip (SoC) designs has been roughly doubling every two years, and this problem is expanding as on-chip functionality increases. The current generation of intellectual property (IP) cores—many of which are based on outdated architectures—were never designed with low-power requirements in mind. By addressing power usage at an early architectural stage, block-level power consumption can be substantially reduced compared to traditional designs. However, while computer-aided design (CAD) tools are available to analyze a power supply network in an IC (e.g., VoltageStorm®, a registered trademark of Cadence Design Systems, Inc., and PowerTheater™ and CoolTime™, trademarks of Sequence Design Inc.), obtaining accurate on-chip data in order to correlate the CAD tools with actual design implementations and to debug issues as they arise remains a challenge.